The present invention relates to a memory device having input and output terminals intended to receive and supply input and output signals, respectively, said device including a capacitive element, a terminal of which constitutes the output terminal of the device and is connected to the input terminal via a switch.
Such devices are currently used in video cameras for generating video signals before signal-processing units, on the basis of signals supplied by light sensors, for example, sensors of the CCD type. Such a sensor supplies a pseudo-periodical signal successively presenting, in the course of the same pseudo-period, a reference level and a video level. It is the difference between these two levels, which constitutes the video signal to be used by the signal-processing unit. A device for generating a video signal thus usually comprises a first and a second memory device intended to memorize the reference and video levels, respectively, in each pseudo-period, and a subtracter intended to implement a difference between said levels.
Such a generating device is described in U.S. Pat. No. 4,987,321. Transistors of the NMOS type constitute the switches used in the memory devices included in the known generating device. The transistors of this type have relatively low switching velocities, of the order of about ten nanoseconds, which implies that the memorization""s can only be correctly carried out for input signals whose frequency does not exceed about 100 MHz. Moreover, when an NMOS transistor is turned on, it has a resistance, referred to as pass-on resistance, whose value is not negligible. By way of example, an NMOS transistor having dimensions which are referred to as standard hereinafter, i.e. having a gate width of 0.5 microns and a gate length of 100 microns, powered under 3 V, will have a pass-on resistance of the order of about 100 Ohms. Such a pass-on resistance generates noise in the memorized signal and thus in the video signal which may be detrimental to a satisfactory exploitation of this signal. This noise may be compensated by choosing NMOS transistors of large dimensions for realizing the switches, but such an embodiment is costly in terms of silicon surface and energy consumption of the generating device.
It is an object of the present invention to remedy these drawbacks to a large extent by proposing a memory device which can operate at relatively high frequencies and generates less noise than the known devices without necessitating a large silicon surface for its realization.
To this end, a memory device as described in the opening paragraph is, according to the invention, characterized in that the switch comprises a first and a second bipolar transistor whose main current paths are arranged head to end between the input and output terminals, the switch also being provided with control means for alternately extracting or injecting the current from or into the bases of the first and second transistors.
The bipolar transistors have switching times which are intrinsically smaller than those of the MOS type transistors and may thus operate at higher frequencies. These switching times are even more reduced because the transistors are current-controlled. The use of two transistors whose current paths are arranged head to end also ensures an optimum current conduction to or from the capacitive element. At similar dimensions, a bipolar transistor has a pass-on resistance which is intrinsically smaller than that of a transistor of the NMOS type and is independent of the energy consumption of said bipolar transistor.
In a particular embodiment of the invention, a memory device as described above is characterized in that the control means include a first and a second controllable current source arranged between the bases of first and second transistors and first and second power supply terminals, respectively, the bases of the first and second transistors being short circuited.
In this embodiment, the first current source controls the conduction of the first and second transistors, while the second current source controls the interruption of said conduction. This interruption is very quick because the second current source directly extracts charges from the bases of the first and second transistors. The first and second current sources are controlled by signals which are generated outside the memory device on the basis of the input signal in accordance with a technique known to those skilled in the art.
In a preferred embodiment of the invention, the memory device comprises means for preventing simultaneous conduction of the first and second current source s.
This embodiment eliminates any possibility of the control signals of the first and second current sources being active at the same time and renders the switch immune to any short-circuit between the two current sources.
In a variant of the invention, the memory device comprises a voltage-regulating element arranged between the output terminal and the bases of the first and second transistors, enabling the amplitude of the base-emitter voltages of the first and second transistors to be limited.
The voltage-regulating element which may be, for example, of the follower type, ensures that the value of the potential of the bases of the first and second transistors is of the same order as that of the DC components of the input and output signals. The amplitude of the base-emitter voltages of the first and second transistors thus remains low, which limits the wear of these transistors and contributes to a longer lifetime of the memory device. Moreover, this regulating element prevents that too strong base-emitter voltages trigger the conduction of the bipolar transistors when the first current source is not conducting.
If the present invention may be used in any type of application involving the memorization of an analog signal, its implementation is particularly advantageous within the scope of processing signals coming from light sensors. The invention thus also relates to a device for generating a video signal, provided with an input intended to receive a pseudo-periodical input signal successively presenting, in the course of each pseudo-period, a reference level and a video level, and an output intended to supply an output signal which is representative of a difference between said levels, said device comprising:
a first and a second memory device intended to memorize the reference and video levels, respectively, in each pseudo-period, and
a subtracter intended to implement a difference between said levels, said device being characterized in that the first and second memory devices are devices as described hereinbefore.
In one of its most advantageous implementations, the invention also relates to an image acquisition device, for example, a video camera or a digital photo camera, comprising:
a device for detecting and converting light into a pseudo-periodical electronic signal,
an input stage intended to receive said electronic signal and to supply a video signal, and
a signal for processing unit intended to exploit said video signal, said acquisition device being characterized in that the input stage includes a generating device as described hereinbefore.
These and other aspects of the invention are apparent from and will be elucidated, by way of non-limitative example, with reference to the embodiment(s) described hereinafter.